A particularly useful (and marketable) feature of data communication transceiver (PHY) chips is the receiver's ability to “frame” its outputs upon recognition of a special framing character in the incoming serial data stream. Framing is used in normal-mode to re-frame data in backplane transceivers and is an integral part of the IEEE 802.3z Gigabit Ethernet and Fiber Channel Standards.
Framing is also used for built-in-self-test (BIST) purposes and to this end many transceiver chips (both backplane and port-SONET/SDH) include a PRBS (pseudo-random bit stream) generator in the transmitter channel and a corresponding verification block in the receiver. The function of the verification block is to determine if the received character matches the framing character. If framing is not achieved, then the verification block requests the deserializer block to “slip a bit” from the incoming serial bit stream and thus move the imaginary frame forward by one bit. This process continues until the character presented at the outputs of the deserializer block matches up with the special framing character and at this point framing is said to be achieved. Irrespective of the application, a common and important requirement for the deserializer circuit in the receiver is the ability to move an imaginary character frame across the incoming serial data stream one-bit at a time until framing is achieved.
FIG. 1 is a diagram that illustrates a basic building block component of a pipelined deserializer that uses each cycle of a divided clock to grab successive bits from a serial bit stream. The basic building block of this architecture is the 1-to-2 DEMUX cell illustrated in FIG. 1. The cell consists of 2 D-type flip-flops (DFF) and a latch. FIG. 2 illustrates the functionality of the cell illustrated in FIG. 1 using waveforms.
As is shown in FIG. 1, incoming data 107 is wired to the data inputs of two DFFs 101 and 103. A negative-edge-triggered DFF 101 on the top row clocks the data on the falling edge of clock 109 thereby capturing the “odd” data bits (see FIG. 2, shown as bits a, c and e that are outputs of the negative-edge-triggered DFF) travelling in a serial bit data stream. The positive-edge-triggered DFF 103 on the bottom row clocks the data on the rising edge of clock thereby capturing the “even” data bits (See FIG. 2, shown as bits b, d and f that are outputs of the positive-edge-triggered DFF) travelling in the serial bit data stream. The output of the DFF 101 on the top-row is then passed to a latch 105. The latch 105 is connected so that it goes transparent when the clock goes high. This effectively delays the “odd” data stream by half a clock cycle (see three bottom waveforms in FIG. 2). The outcome of this half-cycle delay is that the “odd” and “even” data streams are both aligned to the rising edge of the clock at the outputs of the 1-to-2 DEMUX cell (see FIG. 2).
A pipelined deserializer is therefore constructed by connecting 1-to-2 DEMUX cells in a tree-like structure as shown in FIG. 3. FIG. 3 illustrates a configuration of four pipelined stages of DEMUX cells that form a 1-to-16 deserializer 50. As is illustrated in FIG. 3, the data streams out of each stage (n=4 stages) in the pipeline move at half the rate of the data streams moving into that stage. The clock rate for each stage is therefore derived by dividing the clock for the previous stage by two. The simplest implementation of the clock divider is a series of toggle flip-flops connected together to form a 4-bit binary ripple counter. The major advantage of this architecture over other architectures (such as full-rate or half-rate) is that each successive stage performs twice as many demultiplexing operations as the previous stage and each successive stage operates at half the speed of the previous stage. This means that most of the demultiplexing operations are performed at speeds much lower than the top-speed of the block which permits much lower power cells to be used.
FIG. 4 shows a conventional implementation as described in U.S. Pat. No. 5,128,940 of a slip-bit mechanism with a pipelined deserializer architecture 407 such as described in FIG. 3. As illustrated in FIG. 4, this architecture uses an EXOR gate (401a-401c) in the clock path of each stage n of the pipeline. The inputs to each EXOR gate are a respective control signal (403a-403c) and a clock signal for that particular stage. If the control signal to a particular EXOR gate is HIGH then the output of the EXOR gate is the inverse of the clock signal input and if the control signal is LOW then the clock signal is simply buffered by the gate (non-inverted). In a 1:2N demultiplexer (deserializer), 2N types of bit-shifts are required. Importantly, n control signals are required in order to effect these bit shifts.
The disadvantages of these conventional cycle-slip schemes include the necessity of employing N control signals and using a framing verification block that is capable of generating them and the requirement that N (EXOR) gates be used to produce the divided clock signals. It should be appreciated that the use of such gates render such circuits not “correct-by-design”. This is because it is not feasible to perfectly synchronize both inputs to each EXOR gate (the N control signals and the clock signals). When these inputs are asynchronous, then glitches will appear at the outputs of the EXOR gates. Depending on how narrow or wide the glitches are, the effects on the deserializer will vary. These glitches can lead to one or more invalid data characters appearing at the outputs of the deserializer, which in turn can lead to unwanted system effects such as false framing. When the clock to a particular stage in the pipeline gets inverted, then the timing of the data outputs of that stage are correspondingly shifted. Thus to avoid metastability and to ensure the correct operation of successive stages, it is necessary to include N-1 D-Flip-Flops (DFF) along with the N EXOR gates in order to re-synchronize subsequent stages as is illustrated in FIG. 5, thereby introducing more complexity into the clock generation circuitry; See U.S. Pat. No. 5,128,940.